Pipelining

Cairo University Faculty of Engineering Electronics and Communications Department

ELC303A: Computer 3A Computer Architecture 3rd year 2009 – 2010 Eng. Ahmed El-Shafiey

Sheet (1) Pipelining Solution 1- Give two reasons why the speedup from pipelining is less than the number of stages in the pipeline. Explain your answer by mentioning how each of these reasons happen.

Solution:

This question refers to the speedup which may be calculated for N instructions in the program and a clock cycle time of τ as:

0J0 0 0

J

However, this ideal speedup is not realized. Those reasons either increase the CPI from the ideal case of one or increase the cycle time τ. Clocking overhead: In a pipelined processor, there are overheads for latching the data which increase the clock cycle length. Hence, the total execution time will increase and the speedup will not be equal to n. Data hazards (Data dependence stalls): For example, in the case of a simple RISC architecture, a load instruction may produce a value that is used by the following instruction. The second instruction must wait till the load instruction gets the data from the memory. Control hazards (Flushing due to branch misprediction): When we resolve the branch condition we may have to flush the instructions from the mispredicted path. Structural hazards (Hardware stalls ): When two instructions (for example floating point divide) are in sequence and only one divider is available. The second instruction will have to wait for the first to finish. Multi-cycle instructions: These instructions increase the number of stall cycles. Exceptions: Internal and external exception may block the flow of the pipeline.

2- You are going to enhance a machine, and there are two possible improvements: either make multiply instructions run four times faster than before, or make memory access instructions run two times faster than before. You repeatedly run a program that takes 100 seconds to execute. Of this time, 20% is used...