Paper

Problem 3

ANSWER---

Stallall−loads = (((RS1R == RDE) ∗ re1R) + ((RS2R == RDE) ∗ re2R)) ∗ (IRE.op == LW)

It is possible to bypass a load followed by a dependent store since the store doesn’t need the

result of the load until the beginning of its memory stage. For instance:

In some code , data hazards cannot be handled by bypassing.

a load instruction and an immediately following instruction that depends on the load

requiring one stall

* LW R1, 0(R2) [RS1 = R2, RD = R1]

SW R1, 0(R3) [RS1 = R3, RS2 = R1]

Register bypassing or short-circuiting used to eliminate or minimize data hazard stalls.

* LD R1, 0(R2) IF ID EX MEM WB

* MUL R1,R3 ,RS1 IF ID EX MEM WB

* MUL R2,R3,RS2 IF ID EX MEM WB

* ADD RS2,RS1 IF ID EX MEM WB

*

* LD R1, 0(R2) IF ID EX MEM WB

* MUL t R1,R3 ,RS1 IF ID STALL MEM WB

* MUL t R2,R3,RS2 IF STALL EX MEM WB

* ADD RS2,RS1 STALL ID EX MEM WB

PROBLEM 4----

ANSWER----

1. There are only four types of instructions: ALU, BEQZ, LW, and SW.

2. 2. All ALU instructions take 2 cycles of execute, X1 and X2.

3. 3. Branch outcome and target computation take a single cycle, and are performed in the X1

stage.

F D X1 X2 M W

F D X1 X2 M...