Ect 114 Week 2 Activity

Score: ________/30

1. Use your textbook to find the values specified below for the 7400 Series TTL family. (6 points)

7400 series TTL Family |

VOH = 2.4 (Minimum) VOL = 0.4 (Maximum) VIH = 2.0 (Minimum) VIL = 0.8 (Maximum) IOH = -0.4 (Maximum) IOL = 16 (Maximum) Propagation Delay = 60 (Maximum) |

2. Use your textbook to find the values specified below for the 4000B CMOS family. (6 points)

4000B series (+25oC) (VDD = 5V) |

VOH = 4.95 (Minimum) VOL = 0.05 (Maximum) VIH = 3.33 (Minimum) VIL = 1.67 (Maximum) IOH = -0.51 (Typical) IOL = 0.51 (Typical) Propagation Delay = 105 (Typical) |

Note: Signal conditioning may be required when logic states are not compatible when mixing logic families.

VOH of the driver gate must be higher than VIH of the load and VOL of the driver gate must be lower than VIL of the load. The designer must make sure the gates are compatible.

3. Enable means: To activate a circuit and allow the signal through. (1 point)

4. Inhibit means: That you are preventing the signal from passing through. (1 point)

5. For the circuits below, use your knowledge of truth tables to determine the state of the specified inputs in order to get the needed output. The first one is shown as an example.

Example: OUTPUT = CLOCK when ENABLE = _1_

Otherwise, OUTPUT = _0_.

a. (3 points)

OUTPUT = INPUT when GATE = 0

Otherwise, OUTPUT = 0

b. (3 points)

OUTPUT = when PASS = 1

Otherwise, OUTPUT = 0.

c. (4 points)

OUTPUT = A when CONTROL = 0;

Otherwise, OUTPUT = 1.

Sketch the output waveform based on the inputs shown. Use MS Paint or line draw in WORD to sketch your answers. Pay attention to timing.

d. (3 points)

The applied CLOCK will be inverted at OUTPUT when PHASE = _0_

Sketch the output waveform based on the inputs shown.

e. A “BUFFER” is a logic gate that merely passes the input signal. It is intended to isolate the output from the input. (3...