Computer Organisation

1. LOAD X

MAR X

MBR M[MAR] , AC MBR

JMP X

PCX

PCIR[11–0]

2. Connect three one bit register to two one bit register

3. NOT

Truth table

NOT GATE |

A | A’ |

0 | 1 |

1 | 0 |

AND

Truth Table

AND GATE |

A | B | A.B |

0 | 0 | 0 |

0 | 1 | 0 |

1 | 0 | 0 |

1 | 1 | 1 |

OR

Truth Table

OR GATE |

A | B | A+B |

0 | 0 | 0 |

0 | 1 | 1 |

1 | 0 | 1 |

1 | 1 | 1 |

NOR

Truth Table

NOR GATE |

A | B | (A+B)’ |

0 | 0 | 1 |

0 | 1 | 0 |

1 | 0 | 0 |

1 | 1 | 0 |

NAND

Truth Table

NAND Gate |

A | B | (AB)’ |

0 | 0 | 1 |

0 | 1 | 1 |

1 | 0 | 1 |

1 | 1 | 0 |

XOR

Truth Table

XOR Table |

A | B | A XOR B |

0 | 0 | 0 |

0 | 1 | 1 |

1 | 0 | 1 |

1 | 1 | 0 |

4. A 2-to-4 decoder operates according to the following truth table.

S1 | S2 | Q0 | Q1 | Q2 | Q3 |

0 | 0 | 1 | 0 | 0 | 0 |

0 | 1 | 0 | 1 | 0 | 0 |

1 | 0 | 0 | 0 | 1 | 0 |

1 | 1 | 0 | 0 | 0 | 1 |

The 2-bit input is called S1 S0, and the four outputs are Q0-Q3.

If the input is the binary number i, then output Qi is uniquely true.

For instance, if the input S1 S0 = 10 (decimal 2), then output Q2 is true, and Q0, Q1, Q3 are all false. This circuit “decodes” a binary number into a “one-of-four” code.

5. 3 Bit full Adder

Input | Output |

C | B | A | Sum | Carry |

0 | 0 | 0 | 0 | 0 |

0 | 0 | 1 | 1 | 0 |

0 | 1 | 0 | 1 | 0 |

0 | 1 | 1 | 0 | 1 |

1 | 0 | 0 | 1 | 0 |

1 | 0 | 1 | 0 | 1 |

1 | 1 | 0 | 0 | 1 |

1 | 1 | 1 | 1 | 1 |

Truth Table

6. Program to compute Expression z (a+b) * (c – d) * e

LOAD A

ADD B

STORE Z

LOAD C

SUB D

MUL Z

STORE Z

MUL E

STORE Z

7. 4 bit counter with JK flip flop

Binary Counter Count Sequence

Q3 | Q2 | Q1 | Q0 |

0 | 0 | 0 | 0 |

0 | 0 | 0 | 1 |

0 | 0 | 1 | 0 |

0 | 0 | 1 | 1 |

8. D Flip Flop

Truth Table

Clock | D | Qnext |

Rising Edge | 0 | 0 |

Rising Edge | 1 | 1 |

Non Rising | X | Q |