Pipelining

TCS 372A Solution Homework Set #8 - Chapter 12: 4a, 7, 10 Due 11/20/06

Chapter 13: 6, 7

All problems completed

12.4a) Given a 5GHz clocked processor that executes a string move instruction that takes 10 cycles to fetch and decode, and 15 cycles per byte to transfer each byte,

The length of the instruction cycle is:

fetch & decode + number of bytes * cycles to transfer each byte =

10 cycles + (64 bytes * 15 cycles /transfer) = 970 cycles =>

970 cycles / (5 *109 cycles /sec) = 194 * 10-9 = 194 nsec

7) Given a computer with a two stage pipeline,

The following table shows that 4 instructions takes 5 cycles:

| |1 |2 |3 |4 |5 |

|Instruction 1 |FI |EI |  |  |  |

|Instruction 2 |  |FI |EI |  |  |

|Instruction 3 |  |  |FI |EI |  |

|Instruction 4 |  |  |  |FI |EI |

10) A non-pipelined processor has a clock rate of 2.5 GHz and an average CPI of 4.

The machine takes 4 cycles / 2.5 GHZ = 1.6 nsec/instruction

The 5 staged pipeline processor has a clock rate of 2 GHz and an average CPI of 4.

This machine would take:

4 cycles / 2 GHz = 4 nsec/instruction if it were not pipelined.

Being a 5 stage pipelined machine, it has a speed up of up to 5, or takes:

2 nsec/instruct / 5 = .4 nsec/instruct.

It therefore has a speed up of 1.6 / .4 = 4 over the unpipelined machine.

6) Given the code:

LD R1, 0 ;keep value of S in R1

LD R2, 1 ;keep value of K in R2...