Physi

國立東華大學資訊工程系博士班資格考

計算機結構, 2006 Fall

(1) (10%) Please briefly explain: “Compulsory”, “Capacity”, and “Conflict” cache misses.

(2) (20%) How many branch-selected entries are in a (2,2) predictor that has a total of 16K bits in the prediction buffer?

(3) (20%) The design of MIPS (Million Instructions Per Second) provides for 32 general-purpose registers and 32 floating-point registers. If registers are good, are more registers better? List as many as trade-offs as you can that should be considered by instruction set architecture designers examining whether to, and how much to, increase the numbers of MIPS registers.

(4) (20%) For the following code fragment, assume that all data references are shown, that all values are defined before use, and that only b and c are used again after this segment. You may ignore any possible exceptions. The individual statements are numbered to provide an easy reference.

1. if (a>c) {

2. a =b + 10;

3. } else {

4. p = p + 3;

5. q = q * 10;

6. c = p + q;

7. }

8. b = a + q;

List the control dependences. For each control dependence, tell whether the dependent statement can be scheduled before the if statement based on the data references.

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(5) (30%) Your company has a benchmark that is considered representative of your typical applications. An embedded processor under consideration to support your task does not have a floating-point unit and must emulate each floating-point instruction by a sequence of integer instructions. This processor is rated at 120 MIPS (Million Instructions Per Second) on the benchmark. A third-party vendor offers a compatible coprocessor to boost performance. That coprocessor executes each floating-point instruction in hardware (i.e., no emulation is necessary). The processor/coprocessor combination rates 80 MIPS on the same benchmark. The following symbols are used to answer parts (a)-(e):

I – Number of integer instructions executed on the...