Homework 2

1.

[4 pts] Consider a computer implemented using single-cycle (unpipelined) implementation. When the stages

are split by functionality, the stages do not require exactly the same amount of time. The original machine had

a clock cycle time of 10 ns. After the stages were split, the measured times were IF, 1.5 ns; ID, 2.5 ns; EX, 1.5

ns; MEM, 2 ns; and WB, 2.5 ns. The pipeline register delay is 0.2 ns.

a. What is the clock cycle time of the 5-stage pipelined machine?

b. If there is a stall every 4 instructions, what is the CPI of the new machine?

c. What is the speedup of the pipelined machine over the single-cycle machine?

d. If the pipelined machine had an infinite number of stages, what would its speedup be over the single-cycle

machine (assume there are no extra stall cycles.)

2.

[4+4 pts] Consider the following MIPS instructions. This code sequence does not have any delay slot

instruction.

Loop: L.D

MUL.D

L.D

MUL.D

ADD.D

DIV.D

S.D

SUBIU

BNEZ

F0, 128(R1)

F0, F3, F0

F2, 256(R1)

F4, F0, F2

F4, F2, F0

F4, F4, F2

F4, 512(R1)

R1, R1, #8

R1, Loop

The third column in the following table shows the number of cycles of latency between a source instruction (second

column) and any subsequent instruction (of any type) consuming the result of the source instructions. The fourth

column indicates the number of functional units available for executing the respective type of source instruction.

Function Unit

Related Instruction

ALU1

ALU2

Memory Unit

FP Adder

FP Multiplier

FP Divider

SUBIU, BNEZ

L.D, S.D (Address Calculation)

L.D, S.D

ADD.D

MUL.D

DIV.D

Latency Cycles

1

1

3

2

4

8

Number of Units

1

1

2

1

1

1

Assume that the reservation station and the reorder buffer both have infinite size. ALU1 is used for execution of

SUBIU and BNEZ instructions, and ALU2 is used for effective address calculation for load/store instructions.

Assume that you can make at most two writes to CDB in one clock cycle....