Appendix C Solution

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Solutions to Case Studies and Exercises

Appendix C Solutions

C.1

a.

R1

R1

R2

R2

R2

R4

LD

DADDI

LD

SD

DSUB

BNEZ

DADDI

SD

DADDI

DADDI

DADDI

DSUB

b. Forwarding is performed only via the register file. Branch outcomes and

targets are not known until the end of the execute stage. All instructions

introduced to the pipeline prior to this point are flushed.

1

LD

R1, 0(R2)

2

3

4

5

F

D

X

M

W

F

s

s

SD

8

D

X

M

W

s

s

10

11

D

X

M

W

D

X

M

F

s

s

DSUB R4, R3, R2

13

14

15

17

18

X

M

W

D

W

D

X

M

W

F

BNEZ R4, Loop

LD

12

16

F

DADDI R2, R2, #4

9

F

0(R2), R1

7

F

DADDI R1, R1, #1

6

s

s

D

R1, 0(R2)

Since the initial value of R3 is R2 + 396 and equal instance of the loop adds 4

to R2, the total number of iterations is 99. Notice that there are 8 cycles lost to

RAW hazards including the branch instruction. Two cycles are lost after the

branch because of the instruction flushing. It takes 16 cycles between loop

instances; the total number of cycles is 98 × 16 + 18 = 1584. The last loop

takes two addition cycles since this latency cannot be overlapped with additional loop instances.

c. Now we are allowed normal bypassing and forwarding circuitry. Branch outcomes and targets are known now at the end of decode.

1

LD

R1, 0(R2)

DADDI R1, R1, #1

SD

R1, 0(R2)

DADDI R2, R2, #4

DSUB R4, R3, R2

BNEZ R4, Loop

(incorrect instruction)

LD

R1, 0(R2)

F

2

3

4

5

6

7

8

9

10

11

12

13

W

D

X

M

W

F

D

s

X

M

W

F

s

D

X

M

W

F

D

X

M

W

F

D

X

M

W

F

s

D

X

M

F

s

s

s

s

F

D

X

M

14

Copyright © 2012 Elsevier, Inc. All rights reserved.

W

15

16

17

18

Appendix C Solutions

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