Asdas

Assignment 2

Computer Architecture Fall 2015

(10 points)

Question 1) Assume you break up the memory stage into 2 stages instead of 1 to improve throughput in a pipelined datapath.

Thus, the pipeline stages are now: F, D, EX, M1, M2, WB

Show how the instructions below would progress though this 6 stage pipeline. Assuming internal forwarding hardware is available.

LD $5, 0($4)

DADD $7, $5, $5

DSUB $8, $5, $9

Question 2) The five stages of the simple MIPS pipeline are: instruction fetch, instruction decode and register read, execute or calculate address, memory access, and register write. Describe the purpose of each of these stages.

Question 3) Define the terms "structural hazard", "control hazard", and "data hazard" in the context of pipelines. Which of these hazards is addressed by a hardware branch predictor (which guesses whether a branch will be taken or not)? For one of the other hazards, suggest a way, either in software or hardware, the effect of that hazard could be reduced.

Question 4) We begin with a processor implemented in single-cycle implementation. When we attempt to split the processor functionality into multiple pipeline stages, the different stages do not require exactly the same amount of time. Assume that the original single-cycle processor had a clock period of 7 ns. After the stages were split, the measured times were: IF 1.2 ns; ID 1.8 ns; EX 1.4 ns; MEM 1.8 ns, WB 0.8 ns. The pipeline register delay is 0.2 ns.

a. What is the clock cycle time of the 5-stage pipelined machine?

b. If there is a stall every 4 instructions, what is the CPI of the new machine?

c. What is the speedup of the pipelined machine over the single cycle machine?

d. If the pipelined machine had an infinite number of stages, what would its speedup be over the single-cycle machine?

Question 5) In the code fragments below identify the data hazards and describe the number of...