Pipeline Architecture

MIPS Pipeline Architecture

Let’s first discuss MIPS 5-stage pipeline architecture briefly. The 5 stages are: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory (MEM) and Write Back (WB). The IF and ID stages are followed by every instruction because only after instruction decoding do we get to know the real nature of the instruction. This means that PC increment and register fetch always takes place. Hence there are no control signals governing these 2 stages. The control unit generates signals for only EX, MEM and WB stages which are stored in the corresponding pipeline registers and forwarded with every cycle.

The control signals are the same as the ones used for single cycle architecture with the only difference of them being distributed over multiple cycles/stages over here with each one of them being used in either one of the later 3 stages (EX, MEM and WB).

Following is the modified data path and control signal diagrams for the given instructions:

1. Li (Load immediate) loads a constant value into the specified register. Li is a pseudo instruction which means that it is created to help in programming but does not really have an o pcode. So whenever the simulator encounters this instruction, it automatically converts/translates it into addi (with sign extension). As an example consider,

li $8, 10 ; store value 10 in $t8

translates to

addi $8, $0, 10 ; add 10 to value stored in $0 (always zero) and store it in $8

So the data path does not have to be modified from its standard version because of existence of addition operation in the ALU in EX stage.

As mentioned earlier, the control signals in pipeline are the same as the ones used to implement this instruction for single cycle. Only difference being the stages in which these are being used.

The following two diagrams illustrate the modified data path and the corresponding control signal values required.

2. LUI or Load upper immediate: It is an I-type instruction. It loads...