Ee616

Programs:

1. Generate round robin arbiter design verification plan in Excel file format including random & directive random testing scheme in test features. Design Specification is as follows:

a). Bus polling arbiter: e.g. 3 requests from 3 devices on the bus: A, B, C Grant signal: grant[1:0] = 2’b00 for A device grant[1:0] = 2’b01 for B device grant[1:0] = 2’b10 for C device

b). Round robin algorithm:

i. If there is not any request, and then assign grant to A.

ii. If there is only one request, and then assign grant to it.

iii. If there are more requests, consider the last grant

- last grant is A, round robin sequence: BCA

- last grant is B, round robin sequence: CAB

- last grant is C, round robin sequence: ABC

c). Pin list in design: Inputs: clk, rst, reqA, reqB, reqC, Outputs: grant[1:0];

Ans:

module arbiter (clock,reset,reqA,reqB,reqC,grant);

input clock;

input reset;

input reqA;

input reqB;

input reqC;

output [1:0] grant;

reg [1:0] grant;

always@(posedge clock or posedge reset)

begin

if(reqA==0)

begin

grant <= 2'b00;

end

else if(reqB==1)

begin

grant <= 2'b01;

end

else

begin

grant <= 2'b01;

end

end

endmodule

TEST BENCH:

module arbiter_tb();

reg clock;

reg reset;

reg reqA;

reg reqB;

reg reqC;

wire[1:0] grant;

arbiter A (clock,reset,reqA,reqB,reqC,grant);

initial begin

$monitor("clock =%b, reset =%b,reqA =%b, reqB =%b,reqC =%b,grant =%b",clock,reset,reqA,reqB,reqC,grant);

#2 clock =1; reset =1; reqA =0;

#2 clock =1; reset =1; reqB =1;

end

endmodule

2. Print “hello world” in system Verilog code in vim editor with keyword highlighted

function, and put screen shot of running result on your answer sheet.

Ans:

module hello_world ;

initial begin

$display ("Hello World ");

#10 $finish;

end

endmodule