Digital-Pll

Please click on paper title to view Visual Supplement. ISSCC 2008 / SESSION 28 / NON-VOLATILE MEMORY & DIGITAL CLOCKING / 28.6

28.6 A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS

270pH spiral inductor. The CMOS inverter N/P ratio in the LCDCO (as well as the N/P ratios in the ring-DCO tri-state inverters) is optimized for minimum phase noise [5]. The LC-DCO includes 4 binary-weighted NMOS varactors for coarse tuning. An additional 24 equally weighted NMOS varactors are controlled by the shift control box, which addresses an 8 row by 3 column main array. The row-column control logic, placed outside of the DCO, converts the row-column states of the 8×3 array into the 24 cap_hi signals. These signals are similar to the local inv_on signals generated inside the ring-DCO. Finally, 5 more NMOS varactors, the same size as the ones in the main array, are controlled by the 3 dithering and the 2 inc/dec signals. Ring-DCO and LC-DCO open-loop tuning curves as a function of DCO fill factor are shown in Fig. 28.6.4, where fill factor is defined as the ratio of on-state to total main array tri-state inverters for the ring-DCO and low-capacitance-state to total main array varactors for the LC-DCO. All 9 coarse settings of the ring-DCO and all 16 coarse settings of the LC-DCO are measured at 25°C, at various DCO power supply voltages. In both designs, the DCO power supply, VDDA, is separate from that of the digital logic, VDD. The dashed lines in Fig. 28.6.4 show temperature dependency of the tuning range at the highest and lowest coarse settings. The ring-DPLL is operational at power supply values ranging from 0.8 to 1.2V, at 25°C. At 100°C, the 2GHz operation requires a 1.1V supply on both VDDA and VDD. The main figure of merit for a typical ASIC or microprocessor clock generator is the rms and peak-topeak period jitter,. These values define the shortest clock cycle at a given frequency. A measured ring-DPLL period jitter...