Anbumony Vlsi Testing

KASI L.K. ANBUMONY VLSI TESTING TERM PAPER - TEST VECTOR COMPACTION

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A Brief Overview of Test Vector Compaction Methods for Combinational Circuits

KASI L.K. ANBUMONY, GRADUATE STUDENT, AUBURN UNIVERSITY [10], several test set compaction algorithms based on different heuristics are proposed in the literature, e.g. static compaction [1], dynamic compaction [1], independent and compatible fault sets based test generation [2,3,8,9,13], reverse order fault simulation [12], maximal compaction [3], rotating backtrace [3], double detection [8, 9], Two by one [9], Three by two [9], forced pair merging [4] and essential fault pruning [4]. Recent developments show that these algorithms, though successful in producing small test sets, the resulting test sets are still larger than the known lower bounds. This is because of the following two reasons; the above test set compaction_ algorithms are unable to compact the test sets any further, and the known lower bounds are not tight. In order to address both these problems two new test set compaction algorithms, Redundant Vector Elimination (RVE) and Essential Fault Reduction (EFR) [7], are proposed. The rest of the paper is organized as follows. Section 2 briefly describes the concept of test compaction. Section 3 presents the classification of test compaction algorithms. Dynamic Compaction algorithms are described in Section 4. Finally Section 5 presents the conclusions. SECTION 2 CONCEPT OF TEST COMPACTION The concept of test vectors compaction can be defined as follows [1]: Suppose a test T for a stuck-at fault F in a combinational logic circuit C is generated. T consists of logic levels 0 and 1, with some unknown states X (either 0 or 1) being assigned to some primary inputs (PI’s) of C. The PI’s at X may be made known to either a 0 or a 1 without affecting the validity of T. Two tests, T1and T2 (for stuck-at faults F1 and F2 in C), are compactable if each PI of C is: 1) assigned to the same logic level in both TI and...