An Area–Efficient Implementation of Vector–by–Vector Shifter

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An Area–Efficient Implementation Of Vector–by–Vector Shifter

Vasantha Srirambhatla, Santosh Kumar Puram, Ankit Garg, and Sri Raghava Kiran Mukku iKoa Semiconductor India Pvt. Ltd., Hyderabad

 Abstract— Most of the present day DSP processors support Single Instruction Multiple Data (SIMD) architecture, which is very efficient for computation intensive programs. SHIFT is one of the most commonly used operations in DSP algorithms. The present piece of work presents an area–efficient design of shifter logic for vector–by–vector shift operations with variable data width. This also reports the area advantage obtained in this new implementation compared to a traditional barrel shifter.

presented here are with 32 bits of data, with three vector modes (8/16/32 bit operands) supported. The paper focuses on and takes into consideration only the shifter logic and not any other logic that may be associated with it in actual design.

II. TRADITIONAL BARREL SHIFTER In SIMD architecture, for supporting different vector–by– vector shifts, different barrel shifters are required for the three vector modes (8/16/32 bit operands). A traditional way of implementing a barrel shifter for a 32 bit operand with five multiplexer stages is depicted in the Figure 1 given below:

33 bit MUX 33 bit MUX 33 bit MUX 33 bit MUX 33 bit MUX

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Index Terms— Barrel Shifter, SIMD, Vector Operations

I. INTRODUCTION

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OST of the present day DSP processors support Single Instruction Multiple Data (SIMD) architecture, which is very efficient for computation intensive programs. SHIFT is one the most commonly used instructions of the architecture used by DSP programs. The SHIFT instruction can be a right shift or a left shift, and can be either arithmetic or logical. Any SHIFT instruction needs two operands— the data to be shifted and the shift amount. If the operand is made of chunks of varying width (8/16/32 bit), it is called a vector operand. A vector data to be shifted may...