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COMPUTER ARCHITECTURE

CIS – 601

ASSIGNMET 1

SHASHANK SUKKALA

CSU ID - 2571900

C3) A computer is implemented in single cycle implementation, when stages are split by functionality the stages donor require exactly same amount of time. The original machine has a clock cycle of 7ns. After the stages were split, the measured times were, if 1ns; ID 1.5ns; EX 1ns; MEM 2ns; WB 1.5 ns; the pipe line register delay is 0.1ns;

a) What is the clock cycle time of the five staged pipeline machine

Sol: max (length) + overhead

2+0.1= 2.1

b) If there is a stall every 4 instructions , what is CPI of new machine

Sol : CPI = 1(ideal cpi )+Stall cycles

Here there is a stall for every 4 instructions, then stalls =1/4

CPI = 1+ 1/4 = 1.25

c) What is the speedup of the pipeline machine over the single cycle machine

Sol Ideal CPI * Pipeline depth Clock Cycle unpipelined

Speedup = ----------------------------------- * ------------------------------

1+ stall cycle pipelined Clock Cycle pipelined

Ideal CPI =1 ; Pipeline depth = 1; CPI pipelined = 1.25 ns; Clock Cycle pipelined=2.1 Clock Cycle pipelined = 7ns

1 * 1 7

speedup = --------------- * ----------= 7/2.5 = 2.8

1 + 1/4 2.1

d) If the pipe lined machine has an infinite number of stages , what would be the speedup over single-cycle machine.

Sol The speed up factor for instruction pipeline compared to execution without the...