Gpu Architecture

An Analytical Model for a GPU Architecture with Memory-level and Thread-level Parallelism Awareness

Sunpyo Hong

Electrical and Computer Engineering Georgia Institute of Technology

Hyesoon Kim

School of Computer Science Georgia Institute of Technology

shong9@gatech.edu ABSTRACT

GPU architectures are increasingly important in the multi-core era due to their high number of parallel processors. Programming thousands of massively parallel threads is a big challenge for software engineers, but understanding the performance bottlenecks of those parallel programs on GPU architectures to improve application performance is even more difficult. Current approaches rely on programmers to tune their applications by exploiting the design space exhaustively without fully understanding the performance characteristics of their applications. To provide insights into the performance bottlenecks of parallel applications on GPU architectures, we propose a simple analytical model that estimates the execution time of massively parallel programs. The key component of our model is estimating the number of parallel memory requests (we call this the memory warp parallelism) by considering the number of running threads and memory bandwidth. Based on the degree of memory warp parallelism, the model estimates the cost of memory requests, thereby estimating the overall execution time of a program. Comparisons between the outcome of the model and the actual execution time in several GPUs show that the geometric mean of absolute error of our model on micro-benchmarks is 5.4% and on GPU computing applications is 13.3%. All the applications are written in the CUDA programming language.

hyesoon@cc.gatech.edu 1. INTRODUCTION

The increasing computing power of GPUs gives them considerably higher peak computing power than CPUs. For example, NVIDIA’s GTX280 GPUs [3] provide 933 Gflop/s with 240 cores, while Intel’s Core2Quad processors [2] deliver only 100 Gflop/s. Intel’s next generation of...