Cache hierarchy and their testing and implementation techniques on CPU and GPU
Kashyap Mukkamala Srinikhil Mamadapalli
ABSTRACT
Cache memory plays a major role in improving the data access capabilities in CPU and GPU. In this paper we study in detail about the cache hierarchies in both these architectures and analyze in detail how they vary in each of them. The major concern while designing any form of cache is that about increasing the cache hits, in other words it is about reducing the cache misses and the CPU stalls while cache line is fetched from memory. XXXX .Hence for this we study different implementation techniques that allow us to attain higher access speeds and also we will discuss about the tradeoffs of each of these techniques.
For an efficient cache access, the architectures are designed in such a way that the CPUs handle the data access efficiently or else it the developers responsibility to check that the software using the data is efficiently utilizing the current cache architecture and its features. A general analysis of the tradeoffs between these two is studied in this paper and finally we conclude with these cache testing techniques in both CPU and GPU.
TIMELINE
In this project we work together throughout the project and at various stages we share the data collected……….
March 1st: We finish understanding the concepts of cache hierarchies of CPU and GPU, and also reflect upon the complete description and difference at each cache level of GPU and CPU by contrasting their architectures and access speed.
March 29th: Study various implementation techniques that can enhance the access speeds and usage of the cache memory of CPU and GPU.
April 12th: We analyze the various testing techniques of cache utilization on CPU and GPU and contrast between their accuracy.
REFERENCES:
[1] TAP: A TLP-Aware Cache Management Policy for CPU-GPU Heterogeneous Architecture. Presented at the 18th IEEE symposium on HPCA, February 2012
