Vlsi

NAND CMOS Gate

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AND CMOS Gate

NOR CMOS Gate

OR CMOS Gate

2. Discuss the digital design abstraction levels with an example application. (20 points)

• Behavioral level:

–The only thing possible on this level is simulation but typically not synthesizable.

-- Functional description of the model is outlined.

– No system clock and signal transitions are asynchronous with respect to the switching time.

Resource(http://www.engr.uconn.edu/~omer.khan/courses/ece4401_f12/L1.pdf)

• Register level (RTL):

– The design is divided into combinational logic and storage

elements.

– Storage elements (Flip-Flops, latches) are controlled by a

system clock.

– Synthesizable.

• Logic level:

– The design is represented as a netlist with logic gates

(AND, OR, NOT,...) and storage elements.

• Layout level:

Both circuit design and physical design.

3. Discuss the chip fabrication process. (20 points)

Sand

With about 25% (mass) Silicon is -after Oxygen -the second most frequent chemical element in the earth's crust. Sand -especially Quartz -has high percentages of Silicon in the form of Silicon dioxide (SiO2) and is the base ingredient for semiconductor manufacturing.

Melted Silicon

Silicon is purified in multiple steps to finally reach semiconductor manufacturing quality which is called Electronic Grade Silicon. Electronic Grade Silicon may only have one alien atom every one billion Silicon atoms. In this picture you can see how one big crystal is grown from the purified silicon melt. The resulting mono crystal is called an Ingot.

Ingot Slicing

The Ingot is cut into individual silicon discs called wafers. The thickness of a wafer is about 1mm.

Wafer

The wafers are polished until they have flawless, mirror-smooth surfaces. Intel buys those manufacturing ready wafers from third party companies. Intel's highly advanced 32nm High-K/Metal Gate process uses wafers with a diameter of 300 millimeter (~12 inches). When Intel first began making chips, the...