Computer Architecture Pipeline

1) Since the new pipeline has the MEM stage preceding the EX stage, we will not only find that different instructions will execute differently, but we will find new sources of data hazards.

a. Positive change – Loads used immediately before ALU operations can now be removed IF the loads use only register addressing (not displacement or direct), this reduces IC and removes some of the data hazard stalls.

Negative changes: 1. Loads and stores that use displacement or direct addressing will require two operations, also if we need to reuse an item that can now be loaded during an add, the new hardware does not work for us. Consider that we want to do:

DADDM R1, R2, (R3)

Imagine that the value to be loaded by (R3) is to be used again. We cannot load it here and have it saved into a register as this would require two register writes (not to mention that we haven’t been able to name the register that (R3) should be written to). So, in such a circumstance, we will still need to do a LW followed by a DADD. 2. With the EX stage being in the fourth stage, an ALU operation followed by a store requires a stall (see the timing diagram below). 3. There is the potential for a greater branch penalty if we have an ALU operation that computes a condition, followed by a conditional branch (see the timing diagram below).

b. To quantitatively determine if this new pipeline is worthwhile, we need to look at the typical breakdown of instructions and more specifically, how many ALU operations could take advantage of having a data fetch so that we can eliminate some loads. We now have to compare the reduced IC from eliminating loads to the increased IC from the number of loads/stores that use displacement or direct addressing plus the number of stalls introduced from new data and control hazards. Given that the stalls will increase and the net change in IC may be positive instead of negative, this would not be a...