Research in Plc

Master-Slave JK Flip- flop

Master-slave flip flop is designed using two separate flip flops. Out of these, one acts as the master and the other as a slave. The figure of a master-slave J-K flip flop is shown below.

Master Slave Flip Flop

From the above figure you can see that both the J-K flip flops are presented in a series connection. The output of the master J-K flip flop is fed to the input of the slave J-K flip flop. The output of the slave J-K flip flop is given as a feedback to the input of the master J-K flip flop. The clock pulse [Clk] is given to the master J-K flip flop and it is sent through a NOT Gate and thus inverted before passing it to the slave J-K flip flop.

Working

When Clk=1, the master J-K flip flop gets disabled. The Clk input of the master input will be the opposite of the slave input. So the master flip flop output will be recognized by the slave flip flop only when the Clk value becomes 0. Thus, when the clock pulse males a transition from 1 to 0, the locked outputs of the master flip flop are fed through to the inputs of the slave flip-flop making this flip flop edge or pulse-triggered. To understand better take a look at the timing diagram illustrated below.

Master Slave J-K Flip Flop Timing Diagram

TRUTH TABLE |

Input | | Output | Comment |

CLK | J | K | | Q | not-Q | |

↓ | 0 | 0 | | Latch | Latch | No Change |

↓ | 0 | 1 | | 0 | 1 | Reset |

↓ | 1 | 0 | | 1 | 0 | Set |

↓ | 1 | 1 | | Toggle | Toggle | Toggle |

X | 0 | 0 | | Latch | Latch | No Change |

X | 0 | 1 | | Latch | Latch | No Change |

X | 1 | 0 | | Latch | Latch | No Change |

X | 1 | 1 | | Latch | Latch | No Change |

Thus, the circuit accepts the value in the input when the clock is HIGH, and passes the data to the output on the falling-edge of the clock signal. This makes the Master-Slave J-K flip flop a Synchronous device as it only passes data with the timing of the clock signal.

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