Hrtgrt

3.(10 pts) Consider the following instruction sequence:

LD|R1, 40(R2)|||

DADD|R2, R3, R3|||

DADD|R1, R1, R2|||

SD|R1, 20(R2)|||

a. Find all data dependences in this instruction sequence.|||

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Dependency Type|Independent Inst.|Dependent Inst.|Storage Location||

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RAW DADD R2,R3,R3 DADD R1,R1,R2 R2

RAW LW R1, 40(R2) DADD R1,R1,R2 R1

RAW DADD R1,R1,R2 SD R1,20(R2) R1

WAW LD R1,40(R2) DADD R1,R1,R2 R1

WAR DADD R2,R3,R3 LD R1,40(R2) R2

4. (20 pts) Assume the following code fragment is executed using classic 5-stage pipeline MIPS Architecture.

loop: lw|s1, 0(s2)|

addi|s7, s1, 1|

sw|s1, 0(s2)|

addi|s2, s2, 4|

sub|s4, s3, s2|

bne|s4, zero, loop|

a. Show the timing of this instruction sequence without any forwarding. However, you can assume that a register read and write can be done in the same clock cycle. Branches are resolved in X stage of pipeline and the architecture supports branch-taken strategy.

Clock Cycle à|1|2|3|4|5|6|7|8|9|10|11|12|13|14|15|16|17|18|

loop:|lw|s1, 0(s2)|F|D|X|M|W||||||||||||||

|addi|s7, s1, 1|| F| S| S| D| E| M| W|||||||||||

|sw|s1, 0(s2)||||| F| D| E| M | W||||||||||

|addi|s2, s2, 4|||||| F| S| S | D| E| M| W|||||||

|sub|s4, s3, s2||||||| | | F| S| S | D| E| M| W||||

|bne s4, zero,loop|||||||||||| F| S| S| D| E| M| W|

Second Iteration|||||||||||||||||||

loop:|lw|s1, 0(s2)|||||||||||||||||| F|

. . .|||||||||||||||||||||

How many clock cycles does it take to execute one iteration? (The number of clock cycles from ID of first lw to ID of second lw in...