Computer Architecture

B1-a

Miss Rate = 5% = 0.05

Miss Penalty = 105

Hit Rate = 1- Miss rate = 1 - 0.05 = 0.95

Hit Time = Cache Hit x Hit Rate = 1 x 0.95 = 0.95

Average Memory Access Time = Hit Time + (Miss rate x Miss penalty)

Average Memory Access Time = 0.95 + (0.05 x 105) = 6.2 cycle

B1- b

Average Memory Access Time = (Cache Hit x Hit Rate) + (Miss rate x Miss Penalty)

Hit Rate = 64Kb / 256Mb = 0.00025

Miss Rate = 1 – Hit Rate = 1 – 0000025 = 0.99975

Average Memory Access Time = (1 x 0.00025) + (0.99975 x 105) = 0.00025 + 104.97375 = 104.974 cycle

B1- c

The result of the average memory access time with cache is about 105 cycle, but it is 100 cycle with cache disabled. In this case, cache memory doesn’t help the overall performance if we try to access data without locality.

B1-d

G = 100 cycle

L = 5 cycle

100 / (100+5) = 0.951923

There is no point using cache if the miss rate is bigger than 0.951923

B2-a

Cache block | set | way | Mem blocks |

0 | 0 | 0 | M0-M8-M16-M24 |

1 | 1 | 0 | M1-M9-M17-M25 |

2 | 2 | 0 | M2-M10-M18-M26 |

3 | 3 | 0 | M3-M11-M19-M27 |

4 | 4 | 0 | M4-M12-M20-M28 |

5 | 5 | 0 | M5-M13-M21-M29 |

6 | 6 | 0 | M6-M14-M22-M30 |

7 | 7 | 0 | M7-M15-M23-M31 |

B2-b

Cache block | set | way | Mem blocks |

0 | 0 | 0 | M0-M2-M4-M6M8-M10-M12-M14M16-M18-M20-M22M24-M26-M28-M30 |

1 | 0 | 1 | |

2 | 0 | 2 | |

3 | 0 | 3 | |

4 | 1 | 0 | M1-M3-M5-M7M9-M11-M13-M15M17-M19-M21-M23M25-M27-M29-M31 |

5 | 1 | 1 | |

6 | 1 | 2 | |

7 | 1 | 3 | |

B12-

Virtual page accessed | TLB(hit or miss) | Page table(hit or fail) |

1 | Miss | Fail |

5 | Hit | Hit |

9 | Miss | Fail |

14 | Miss | Fail |

10 | Hit | Hit |

6 | Miss | Hit |

15 | Hit | Hit |

12 | Miss | Hit |

7 | Miss | Hit |

2 | Miss | Fail |