Cpe 341 Analysis

Exercises:

1: There is no Clk input for the SR latch. If we consider an input at either the S or R terminal to change the state we may then construct a State Table and State Diagram. Do this for NAND SR latch.

For the State Table,

S | R | Q(t + 1) |

0 | 0 | Undefined State |

0 | 1 | 1 |

1 | 0 | 0 |

1 | 1 | Q(t) |

The RS NAND latch is an active-low circuit, thus it gives the inverse Next State with respect to the original characteristic table of an SR flip-flop

For the State Diagram,

2: A T flip-flop may also be formed from a D flip-flop and an XOR gate, implementing the relation D = T XOR Q. Create a state table and draw a state diagram for this configuration. Compare your results with the J-K implementation of the previous exercise.

For State Table and Diagram,

Q(t) | T | Q(t + 1) |

0 | 0 | 0 |

0 | 1 | 1 |

1 | 0 | 1 |

1 | 1 | 0 |

3: From Fig. 6.10 show that the D input may be expressed as D = JQ' + K'Q.

State Table

J | K | Q(t) | Q(t + 1) | D |

0 | 0 | 0 | 0 | 0 |

0 | 0 | 1 | 1 | 1 |

0 | 1 | 0 | 0 | 0 |

0 | 1 | 1 | 0 | 0 |

1 | 0 | 0 | 1 | 1 |

1 | 0 | 1 | 1 | 1 |

1 | 1 | 0 | 1 | 1 |

1 | 1 | 1 | 0 | 0 |

ZD

D = K'Q + JQ'

4: From the state table shown at right, create a state diagram. Draw a hardware diagram corresponding to the state table using D flip-flops.

No table shown.

5: For the state table shown below at right, complement the Out and Next values. Then draw the corresponding state diagram. Also draw a corresponding hardware diagram using D flip-flops.

Present | | Next | |

A | B | X | A | B | Out |

0 | 0 | 0 | 0 | 0 | 0 |

0 | 0 | 1 | 0 | 1 | 0 |

0 | 1 | 0 | 0 | 0 | 0 |

0 | 1 | 1 | 0 | 1 | 0 |

1 | 0 | 0 | 0 | 0 | 0 |

1 | 0 | 1 | 1 | 0 | 0 |

1 | 1 | 0 | 0 | 0 | 1 |

1 | 1 | 1 | 1 | 0 | 1 |

Complementing,

Present | | Next | |

A | B | X | A | B | Out |

0 | 0 | 0 | 1 | 1 | 1 |

0 | 0 | 1 | 1 | 0 | 1 |

0 | 1 | 0 | 1 | 1 | 1 |

0 | 1 | 1 | 1 | 0 | 1 |

1 | 0...