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numbers of Intellectual Property (IP) cores are connected to the communication fabric (router based network) using network interfaces. The network is used for packet switched on-chip communication among cores. It supports high degree of reusability and scalability. In this work a scalable network based on Mesh of Tree (MoT) topology has been presented. MoT interconnection network has the advantage of having small diameter as well as large bisection width and has a nice recursive structure. These characteristics make it more powerful than other interconnection networks like meshes and binary trees. A generic NoC simulator is designed for performance evaluation in terms of network throughput, latency and power of different topologies under different traffic situations. In this work, We design Table Based Routing Scheme to take on any arbitrary topologies and finally design a Application Specific NoC Simulator . Routing Schemes are implemented and compared with previously available mapping strategies. Adaptive Routing Technique – Odd-Even Model is discussed and performance is evaluated

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Contents

Contents ........................................................................................................................................................ 5 List of Figures…………………………………………………………………………………………………………………………………………..6 Nomenclature ............................................................................................................................................... 7 1 Introduction ............................................................................................................................................... 8 1.1: Network on Chip ................................................................................................................................ 9 Communication Model of NoC ................................................................................................................. 9 Description of...