# Testing

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Date Submitted: 03/26/2014 06:19 PM

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- Homework 4

[3]

a)

This would equal the time of stage with the maximum length plus the pipeline register delay

2 + 0.1 = 2.1

b)

This would be 1 + cycle stalls, where cycle stalls = .25 (one every four instructions)

CPI = 1 + .25 = 1.25

c)

speedup = 7/2.1 = 3.33

d)

[6]

a)

we can rearrange the [IF ID EX MEM WB] to [IF ID MEM EX WB]

b)

Source Destination

MEM MEM -if there is a load to store conflict

EX MEM -if there is ALU operation that needs to be Load or Store

EX EX -if there is ALU operation to ALU operation

c)

There would have to be a stall in the cases of loading and storing directly after an ALU instruction

e.g. – ADD F2, F4, F6

LD F3(F2)

e.g. – ADD F2, F4, F6

SW F2(F3)

d)

Original New

LD F1, 4(F2) ADDI F4, F2, 4 -This must take two instructions now

LD F1(F4)

LD F1, 0(F2) ADD F3, F4, (F2) -This can be reduced to only one instruction

e)

The difference in CPI would be from stalls within the instruction set. In the original it is a Read after Write operation that will produce a stall; however this is not a problem in the new pipeline arrangement. On the other hand a ALU instruction who writes to a register that is used to compute the address of say a load instruction would create a stall in the new pipeline arrangement where there would be none in the original

[12]

a)

Instruction | IF | ID | EX | MEM | WB |

LD | 1 | 2 | 3 | 4 | 5 |

MUL.D | 2 | 3 | 4-10 | 11 | 12 |

LD | 3 | 4 | 5 | 6 | 7 |

ADD.D | 4 | 5 | 11 - 14 | 15 | 16 |

SD | 5 | 6 | 17 | 18 | 19 |

DADDIU | 6 | 7 | 8 | 9 | 10 |

DADDIU | 7 | 8 | 9 | 10 | 11 |

SGTIU | 8 | 9 | 10 | 11 | 12 |

BEQZ | 9 | 10 | 11 | 12 | 13 |

First instruction enters at cycle 5, and last at 19 -> 19-5 = 14 cycles

b)

Instruction | Issue | Read | Execute | Write |

LD | X | x | X | X |

MUL.D | X | X | X | |

LD | X | X | X | X |

ADD.D | X | X | | |

SD | X | X | X | X |

DADDIU | X | X | X | X |