Uart Ic

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Category: Science and Technology

Date Submitted: 09/15/2012 12:52 AM

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In the modern era, communications are all made possible through electronic means. But data communication through a channel are vulnerable to noise and interference and thereby prone to errors. In precision communication systems handling important data these errors due to noises are highly unacceptable. The errors which might be caused due to channel inefficiency should be minimized and corrected within the communication system itself.

Here in this project we are trying to design and implement a serial communication interface system which transmits a four bit data and can detect and correct errors up to two bits. To implement the fore said system we realize a Hamming encoder followed by a FIFO register in the transmitter section and a hamming decoder with a serial to parallel converter in the receiver part. In our system transmission errors up to two bits can be detected and one bit error can be detected and corrected.

The platform chosen to carry out the project is on VLSI, where the system is designed and coded using a hardware description language which is then implemented on a field programmable gate array (FPGA). Thus the particular FPGA works as our designed system.



The fundamental parts of an SCI system are the transmitter and the receiver. But for faithful transmission of data, that is minimizing transmission errors by detecting and correcting them, if any, a proper error detection scheme should be employed, which in this case is a Hamming error detection scheme.

The basic operation of an SCI system includes accepting the data bit sequence to be transmitted which, in here, is transmitted in blocks of 4 bits and transmitting the data serially in accordance with the rate fixed by the system clock and the clock divider subroutine. The serially transmitted data is accepted by the receiver and the data sequence is delivered as parallel bit stream of 4 bits.

By incorporating the Hamming...