Solving Architecture

ECE586 Homework No. 3 Solution

Problem No. 1

(a) The clock period for the pipelined processor is decided by the longest pipeline stage (1.75 ns for the EX stage) Pipeline register delay = 0.25 ns Therefore: Clock period for pipelined processor = 1.75 + 0.25 = 2 ns Clock rate = 1 / Clock period = 0.5 GHz (b) Ideal CPI = 1 The processor needs to incur a 2-cycle stall after every 6 instructions. Therefore: Effective CPI = 1 + (1/6)(2) = 1.33 (c) Speedup =

( ( ) )

For the single-cycle processor: Clock period = 6 ns, CPI = 1 For the pipelined processor: Clock period = 2 ns, CPI = 1.33 Therefore, Speedup = = 2.25

Problem No. 2

(a) 1st Instruction LOAD LOAD ADD OR LOAD OR ADD 2nd Instruction ADD OR OR SUB OR SUB SUB Register R1 R1 R6 R3 R3 R6 R6 Type of Dependence RAW RAW RAW RAW WAR WAR WAW

(b) Pipeline diagram without forwarding:

Clock Cycle Instruction LOAD ADD OR STORE SUB 1 IF 2 ID IF 3 EX ID IF 4 MEM stall stall 5 WB stall stall EX ID IF MEM stall stall WB stall stall EX ID IF MEM EX ID WB MEM stall WB EX MEM WB 6 7 8 9 10 11 12 13 14

(c) Pipeline diagram with forwarding: Clock Cycle Instruction LOAD ADD OR STORE SUB 1 IF 2 ID IF 3 EX ID IF 4 MEM stall stall 5 WB EX ID IF MEM EX ID IF WB MEM EX ID WB MEM EX WB MEM WB 6 7 8 9 10

(d) Non-pipelined: Each instruction takes 5 cycles. There are 5 instructions in the sequence. Execution time = 5 * 5 = 25 cycles Pipeline without forwarding: Execution time = 14 cycles (shown in the part (b) pipeline diagram) Pipeline with forwarding: Execution time = 10 cycles (shown in the part (c) pipeline diagram) Therefore: Speedup without forwarding compared to non-pipelined execution = 25/14 = 1.786 Speedup with forwarding compared to non-pipelined execution = 25/10 = 2.5

Problem No. 3

(a) 1st Instruction OR OR LOAD AND 2nd Instruction LOAD STORE STORE OR Register R3 R3 R4 R7 Type of Dependence RAW RAW RAW WAR

(b) Pipeline diagram without forwarding: Clock Cycle Instruction OR LOAD AND STORE 1 IF 2 3 4 MEM...