Formal Report

Table of Contents

OBJECTIVES 2

INTRODUCTION 2

MATERIALS 2

PARTS 2

PROJECT DESIGN 2

TEST RESULTS 4

CONCLUSIONS 4

Table of Figures

Figure 6.1 State Diagram of Traffic Controller………………………………………………………………………………

Figure 6.2 Plan for Traffic Light Controller Operation…………………………………………………………………..

Figure 6.3 Traffic Light States……………………………………………………………………………………………………….

Figure 6.4 Block Diagram……………………………………………………………………………………………………………..

Figure 6.5 VHDL File……………………………………………………………………………………………………………………..

Figure 6.6 Simulation(s)………………………………………………………………………………………………………………..

Objectives

1. To analyze a real world problem in terms of how system inputs and the present state determine the next output state using a state diagram.

2. To implement a solution using state diagrams, VHDL and FPGA

Introduction

Finite state machines are systems that output a sequence of pre-defined states. The order of the states within that sequence may change as system inputs vary. State diagrams help us to analyze the various ways a system can progress through its output states. Each state can contain one or more unrelated variables, such as voltage, pressure, speed and so forth.

Materials

IBM PC or Compatibility with Windows 2000 or Higher

Quartis II Design Software-Version 9.1

Parts

eSOC III Board

Project Design

Figure 6.1 State Diagram of Traffic Controller

Figure 6.2: Plan for Traffic Light Controller Operation

State Colored LEDs

Time in This State

N-S Green 5 sec.

N-S Yellow 1 sec.

E-W Green 5 sec.

E-W Yellow 1 sec.

Figure 6.3 Traffic Light States

Figure 6.4 Block Diagram

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-- Create Date: 20:17:51 02/14/2014

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-- Module Name: traffic - Behavioral

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