Pipeline

This Unit: (Scalar In-Order) Pipelining

App App App

•! Basic Pipelining

•! Pipeline control

System software

CIS 501 Computer Architecture

Unit 6: Pipelining

Mem

CPU

I/O

•! Data Hazards

•! Software interlocks and scheduling •! Hardware interlocks and stalling •! Bypassing

•! Control Hazards

•! Branch prediction

CIS 501 (Martin/Roth): Pipelining

1

CIS 501 (Martin/Roth): Pipelining

2

Readings

•! H+P

•! Appendix A

Datapath and Control

+ 4 PC

I$

Register File

s1 s2 d

D$

control

•! Datapath: implements execute portion of fetch/exec. loop

•! Functional units (ALUs), registers, memory interface

•! Control: implements decode portion of fetch/execute loop

•! Mux selectors, write enable signals regulate flow of data in datapath •! Part of decode involves translating insn opcode into control signals

CIS 501 (Martin/Roth): Pipelining 3 CIS 501 (Martin/Roth): Pipelining 4

Single-Cycle Datapath

Multi-Cycle Datapath

+ 4 PC

+ 4

I$

Register File

s1 s2 d

PC

I$

D$

Register File

s1 s2 d

A O B D

D$

•! Single-cycle datapath: true “atomic” VN loop

•! Fetch, decode, execute one complete insn every cycle •! “Hardwired control”: opcode to control signals ROM +! Low CPI: 1 by definition –! Long clock period: to accommodate longest insn

CIS 501 (Martin/Roth): Pipelining 5

•! Multi-cycle datapath: also true “atomic” VN loop

•! Fetch, decode, execute one complete insn over multiple cycles •! Micro-coded control: “stages” control signals •! Allows insns to take different number of cycles (the main point) ±! Opposite of single-cycle: short clock period, high IPC

CIS 501 (Martin/Roth): Pipelining 6

Single-cycle vs. Multi-cycle Performance

•! Single-cycle

•! Clock period = 50ns, CPI = 1 •! Performance = 50ns/insn

Latency vs. Throughput

insn0.fetch, dec, exec

Single-cycle

insn0.fetch insn0.dec insn0.exec

insn1.fetch, dec, exec insn1.fetch insn1.dec insn1.exec...